RISC-V.JS
Implementation of RISC-V 32I ISA in JS!
Console:
Input buffer:
Register view:
Memory view:
Testbench:
00a_unimp
00b_unimp
00c_unimp
00d_unimp
00e_unimp
00f_unimp
00g_unimp
00h_unimp
00i_unimp
01_lui
01_no_hazards
02_addi
02_all_data_hazards
03_add
03_all_control_hazards
04_all_hazards
04_bne
05a_jal
05b_jal
06_auipc
07a_lb
07a_lh
07a_lhu
07a_lw
07b_lb
07b_lbu
07b_lh
07b_lhu
07b_lw
08a_sb
08a_sh
08a_sw
08b_sb
08b_sh
08b_sw
09a_jalr
09b_jalr
09c_jalr
10a_ops
10b_ops
11_opimms
12_branches
add32
addi
add
and32
andi
and
auipc
beq
bge
bgeu
blt
bltu
bne
bpred_bht
bpred_j_noloop
bpred_j
bpred_ras
cache
hello32
jal
jalr
j
lb
lbu
lh
lhu
lui
lw
matmul32
mnist_fast
mnist_test10
mnist_test1
mnist_test20
mnist_test5
mul32
mul32_test
mul64_test
or32
ori
or
packmul_test
quicksort
reverse32
sb
sh
simple
slli
sll
slti
slt
srai
sra
srli
srl
sub32
sub
sw
thelie32
thuemorse32
xor32
xori
xor
echo32
Max Speed (Hz):
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Custom assembly (simple instructions only):
Loaded hex or dump: